Advanced packaging - a challenge for the whole industry

Basics of an emerging technology

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Area arrays (contact or bond bumps on the bottom of a chip) for use on SMT boards drive the packaging technology to a remarkable growth. Eventually, advanced packaging will reshape the entire industry. Advanced packaging refers to both devices comprising several components or assembled using unusual bonding techniques. The benefits are minimized size and signal propagation time, and often the cost-efficient solution to an otherwise tricky problem.

Helmut Rutterschmidt, Managing Director, Datacon, Austria

In the usually applied IC packaging technology, the semiconductor chip is die-bonded to a lead frame, and is connected electrically by wire bonds. It is then encapsulated in a plastic material and the interconnections are trimmed and shaped. As the widely used QFPs, PLCCs, SOs and other packages derived from them, this is currently the predominant technology in a wide range of applications. To give an idea: in 1996, the IC market totalled 53bn pieces. The forecast for 2001 is 83.3bn devices, of which 10bn will be advanced packaging products.
Advanced packaging combines semiconductor and SMT (surface mount technology), resulting in products that are smaller, cost less, and have improved characteristics and higher integration levels. In addition, the number of interconnections can be reduced. A plastic BGA with flip-chip assembly could contain several chips that are mounted on a glassfiber-reinforced substrate using high-melting solder bumps. Eutectic solder bumps are used between the substrate and the board. In general, the packages are very small. Flexible circuits or laminated substrates replace the lead frames. The chips are interconnected with solder bumps or conducting bonds instead of wires, and contact between the package and the board is via area array pins or solder bumps. The final package can contain both semiconductor and passive components.
Flip chip on board and chip on board
The FCOB (flip chip on board) technique has been used by Delco and IBM for more than 30 years in an effort to satisfy customer demand for smaller automotive devices or faster computers, respectively. The C4 (controlled collapsed chip connect) was the first successful flip chip process, capable of both mechanical and electrical interconnections of a chip with a ceramic substrate by solder bumps. A high production yield resulted in part from the surface tension of the melted solder bumps that caused the chip to align itself automatically on the substrate. Technologies were subsequently developed that allowed FCOB to be mounted on low-cost glassfiber-reinforced epoxy resin boards (FR-4). However, FR-4 and silicon have different heat expansion coefficients, so that temperature change produces mechanical stress that tended to weaken the IC interconnections. This problem was solved by applying an epoxy underfill that distributes the forces and thus stabilizes the interconnections.
There is a bright outlook for FCOBs, because of benefits such as reduced manufacturing steps, improved electrical characteristics and miniaturization. In addition, overall capital investment is lower, since the latest generation of die bonders can handle both flip chip pick-and-place from wafer and flux/bonding applications in one machine. The COB (chip on board) technology is similar to the FCOB process with the difference that the interconnections are on the chip face, necessitating wire bonding. Both processes require a machine that places the dice on the substrate. In choosing their equipment, manufacturers should make sure the equipment can later be upgraded.
Bump interconnect technology
Bump interconnect technology (BIT) uses the same equipment and materials as in backend IC assembly. The gold-bumped wafers are interconnected with the substrate, using a conductive epoxy resin filled with silver. The BIT process solves the problem of slow-flowing epoxy underfill, but still requires the underfill before the flip chip is placed. The gold bumps do not contract as in the case of the C4 process. Instead, they are flattened and covered with a small amount of conductive adhesive. This displaces the underfill and provides the electrical interconnection between chip and board. With no possibility of self-alignment, the chips must be placed very carefully and precisely.
Multichip module (MCM)
MCM technology combines two or more chips on a FR-4, ceramic or silicon substrate. Introduced some years ago, MCM has been the technology of choice for a number of application areas. The technology dramatically increases integration density, but chip handling requires special care to ensure that the modules satisfy stringent quality requirements. Direct wafer placement with automatic wafer changing and mapping is especially recommended for multi-chip/multi flip-chip applications, because of the lower costs and high quality requirements. For MCMs, the chip quality is of primary importance as just one defective chip turns the whole module into scrap.
Chip scale packages
Chip scale package (CSP) is a term used for an encapsulation that is no more than 20% larger than the chip itself. CSPs are a third of the size of conventional QFPs with a large number of interconnections. They offer benefits in price, density, assembly yield and performance. This technique also solves the problem of testing encountered with FCOB, COB and MCM – all technologies that process dies. Like standard ICs, CSPs are packages that can be mounted in sockets or burned-in.
Some CSPs are designed to behave like flip-chip mounted devices without underfill. The tab-like connections and elastomer adhesive are flexible, so that the different temperature coefficients of substrate and package are not a problem and no underfill is necessary. For instance, the µBGA is a chip that is mounted mechanically on a flexible circuit using elastomer adhesive, with the electrical interconnections produced by means of S-shaped tabs. The flexible board ensures that the I/Os on the IC’s bond pads are redistributed to a standard array of eutectic bumps. These are supported by elastomer spacers and move relatively freely without having up mechanical stresses in the bumps. Above all, CSPs allow the standardization of interconnection arrays that remain stable, independent of vendor and degree of downsizing.
Connection with Z-axis material
A very promising packaging technology, with some similarities to flip-chip process, uses so-called Z-axis material for interconnections. It is based on conductive adhesives, either liquid or film. The Z-axis material consists of small, spherical insulating shells with conducting contents. To form the interconnection between the bumps and the chip, the die bonder must be able to apply a pressure, called bond force, to the chip. Under the high local pressure, the spheres between bumps and pad collapse to form a conducting path. This eliminates the need for special leads from the chip to the substrate. While this technology is potentially very interesting, it is still new and has some disadvantages, such as no self-alignment ability, for instance.
Other packaging technologies
LOC (lead on chip) and COL (chip on lead) are other packaging technologies currently being introduced. They both use conventional wire bonding for the electrical interconnections between the chip and a smaller lead frame. In the case of LOC, shorter leads result from routing the connections from the face near the central axis of the chip (instead of from the edge). In the case of COL, the chip is interconnected to the lead frame by means of very short bond wires on the chip bottom, giving outstanding electrical characteristics. LOC and COL packages are only marginally larger than the chips themselves. It is too soon to say whether one of these technologies will some day dominate the industry. Common to all is the need for exact chip placement. Additional process steps may be required to interconnect the chip with the substrate.Modern packaging is a combination of semiconductor and SMT assembly technologies. Market requirements are such that chip processing will no longer be done solely by semiconductor manufacturers or packaging specialists. Some backend areas in the industry are already under pressure to combine SMT assembly and raw chip processing – whether COB, FCOB or hybrid technologies – in a single production step. Equipment manufacturers have to get ready to handle all these packaging technologies. The advanced packaging philosophy is: smaller, faster, and lower cost.
Equipment for advanced packaging technologies
Sorting and packing dice from the wafer into SMD packaging (tape, surfetape) is cost-intensive. In other words, chip processing slows a high-speed pick&place machine designed for highest throughput. Production records for COB/hybrid technology also show that repeated handling or touching of the dice can significantly affect the quality of the chips. At the same time, more demanding design rules, higher complexity or micromechanical functions on the surface (sensors) are making chips increasingly susceptible to damage. The use of alternate chip carriers such as waffle or gel packs has not proved conductive to high-volume production.
The manufacturer needs to keep investment in new fields like cleanroom and new machinery cost-effective, but also to continue to output high-quality products. Care has to be taken that using special technologies does not end-up restricting the speed of a production line. Manufacturers must ensure that both their suppliers and the equipment are completely future-proof. Increasingly, manufacturers who are planning investment in equipment are focusing on the following points:
• Modularity (mechanical, open control architecture, easy upgradability to hardware and software options to control all processes, subsequent boosting of production output)
• Flexibility (ability to use equipment as stand-alone machine or part of a line)
• Precision (to meet the increasing demands of flip-chip technology)
Recent forecasts predict that, by the year 2006, portable consumer products will make up 60% of manufactured systems. No doubt, all of these will contain some form of advanced packaging technology.
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Noch gehören sie zu den magischen Begriffen der kommenden Generation von ICs und Baugruppen, die Advanced-Packages. Flip-Chip, Chip-on-Board, Chip-Scale-Integration usw. treiben die Elektronik weiter voran zu noch höherer Leistungsfähigkeit bei weiter eingeschränkten Abmessungen. Die Herausforderungen sowohl an Hersteller der Packages als auch an Anwender sind hoch. Hier ein Abriss der technischen Grundlagen.
Les Advanced-Packages font encore partie des mots magiques de la prochaine génération de CI et de modules. Flip-Chip, Chip-on-Board, Chip-Scale-Integration, etc. font progresser l’électronique dans le sens d’un accroissement des performances et d’une réduction des dimensions. Les fabricants et les utilisateurs sont face à des défis de taille. Voici un aperçu des principes techniques.
Appartengono ancora al magico concetto della generazione emergente della Ics ed elementi costruttivi. Gli Advanced-packages Flip-Chip-on-Board, Chip-Scale-Integration ecc. portano l’elettronica ulteriormente all’avanguardia di ancora più alte prestazioni nella misura ulteriormente limitata. Le sfide ai produttori come pure agli utenti sono impegnative. Qui di seguito, un abbozzo delle basi tecniche.
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