Flip chip (FC) technology is gaining an increased level of importance for a variety of applications based on its board application or in packaging process. Driving forces for the introduction are the increase of speed and performance along with higher I/O count, and a cost reduction. For this, it is essential to use low-cost bumping techniques togheter with an assembly method compatible to existing SMT processes.
T. Oppert, E. Zakel, T. Teutsch, PacTech Technologies, Berlin, Germany
For nearly all existing FC techniques a bump formation on the chip I/O is needed. Established techniques like the C4 process do not fulfill the cost requirements for low-cost products. A selective chemical plating method can reduce bumping cost significantly since it does not require masking or metal sputtering. Additionally, this technique easily allows a parallel processing of multiple wafers, leading to a high throughput. In the FC assembly the Ni bumps fulfill the following function: they protect the Al surface and act as an adhe-sion layer and a diffusion barrier, and guarantee a stable and reliable contact to the Al bondpads. This is mainly the function of an under-bump metallization (UBM), besides, the Ni can also offer a stand-off, e. g. for chip on glass (COG) using ACF.
Bumping is an important technology for flip chip in package applications like BGAs and especially chip-size packages. The electroless nickel bumping process is key for these applications. Especially the function of an additional corrosion protection by the low-cost nickel under-bump metallization (UBM) is an important reliability improvement. The TUB/IZM institut in Berlin has developed an electroless Ni/Au bumping process that has been implemented into a packaging method by Pac Tech.
An additional important aspect of electroless-nickel bumping is the simplicity of the process steps. Therefore, it can be implemented logistically in the manufacturing process as last step of the wafer processing. In this case, electroless-nickel is an integral part of the frontend processing. Due to the incompatibility of the used chemicals in the semiconductor process, electroless-nickel can be implemented as a part of the probing and electrical testing respectively burn-in facility. In this case, a closed fully automatic system is possible allowing the engineers in these facilities to handle the process. Another opportunity is the implementation of electroless-nickel bumping as a part of the backend engineering. Especially with the increased relevance of flip-chip in package (FCIP) applications, an implementation of this process as an integral part of a subcontractor assembly facility is possible.
Therefore, interesting developments and discussions between frontend and backend engineering takes place. The advantage of the implementation of nickel bumping in the frontend processing is given by the possibility of an optimal combination with electrical testing and burn-in. On the other hand, the improved test together with improved wafer qualities can potentially offer solutions for known-good-die (KGD) in the near future. An optimally tested die, which does not necessary need burn-in, allows an implementation of bumping in the backend engineering.
Electroless Ni/Au bumping
The advantages of bumps for flip-chip in packages are the cost saving potential due to assembly, the increased reliability, the improved electrical performance, and the improved thermal management. Following the Ni bumping, a selective solder application on the wafer or the substrate is necessary to prepare for for FC soldering. The stencil printing of solder paste has highest potential for cost reduction in FC assembly. The electroless-Ni and the Ni solder FC interconnection system is investigated with regard to solderability, mechanical properties (adhesion) and resistivity. All investigations are related to eutectic (Pb37%Sn63%) or near eutectic solder (2%Ag). The chemical bumping process is wet-chemical and maskless. With this manufacturing process, all types of wafers can be bumped with a standard procedure in good quality. In a bumping line, wafers from 100 to 200mm diameter can be plated. The key for a successful and reproducable manufacturing process is in the chemicals and equipment. The electroless-nickel bumping can be performed with standard chemicals available on the market for simple test structures and test dies without electrical inner circuitry. However, when applied to functional wafers with complex electrical structures, different metallization and different passivations, the process requires specific proprietary chemical compositions for a reproducible and reliable result.
Electroless-nickel is used in industry for a series of applications in which Al work pieces are plated with Ni. The equipment available for these standard processes, based on large work pieces or PCBs, is not suitable for wafer bumping. To fulfilll the specific requirements for wafer bumping, a new modular electroless-Ni wafer bumping line has been developed. Each module can take batches of 25-wafers (200mm).
Ni bumping process steps
First, to prevent Ni plating, the wafer backside has to be covered by a stable resist prior to the chemical bumping process. The next step is a treatment in an Al cleaner, which removes oxide layers, while the Al surface is micro-etched. An alkaline zincate solution is used for activating the Al surface. For the electroless-Ni plating, a bath based on sodium hypophosphite is used. The rate of Ni deposition is 20µm/h. A final Au coating on the Ni is necessary to prevent oxidation and enables long-time solderability of bumps. A maximum Au thickness of 0.25µm can be achieved. The quality of bumps is controlled by optical microscopy, profilometer measurements and shear tests.
The minimal bump height is 1µm to have a closed and void-less Ni-layer. The maximal height is limited by the pad to pad spacing. The bump height must not be larger than ½ pad spacing (plus 10µm for safety) to avoid short circuits between neighboring pads by overgrowing Ni. A height of 5µm is recommended for FC soldering. This meets the requirements of reliability and fast processing. The adhesion of the bumps on the Al pads depends on the pad area. For 100 x 100µm pads, the shear strength is at least 100g. A thin Au cover layer protects the Ni from oxidizing and keeps it solderable. It can be adjusted to up to 0.25µm. The uniformity of bump height is 2% on 100mm wafers and 4% on 200mm wafers, which is sufficient for nearly all types of applications.
Wafer design rules
Based on the experience gained by the processing og several types of wafers, design rules have been defined. As pad materials, AlSi1%, AlSi1% Cu0.5%, AlCu2% and other alloys of these metals were investigated. All types have been processed with good results. Nevertheless, there are some restrictions on the wafers to be Ni bumped. The Al bondpad should be 1µm or more to have sufficient Al thickness after cleaning and activation. There are no limits to passivation thickness, but the passivation must be free of defects. Cracks cause a growth of Ni that can produce shorts. This will also occur on parts of a wafer surface which were scratched by improper handling. Ni also grows on Si that is not covered by an oxide or passivation. Unprotected Si in the wafer scribe line will cause plating of a Ni layer with low adhesion. Therefore, the scribe line should be almost insulation (thin thermal oxide is sufficient), except for defined process control structures. Furthermore, the pad spacing has to be at least 20µm to prevent shorts by overgrowing Ni.
Bumping manufacturing process
For solder application two methods are used: solder paste printing and placement of pre-formed solder balls (solder ball bumping technique SB2). For solder paste application a printing machine is used. For a manufacturing process of wafer-level stencil printing, a special workholder and wafer handling system was developed. Typical solder pastes are PbSn63 or PbSn61Ag2 alloys with particle sizes below 20µm. The stencil apertures are adapted to the specific application. The volume of the printed paste is determined by the aperture diameter and stencil thickness. The selection of appropriate stencil geometry is essential for printing with high yield. Special design rules have been developed for this process. The subsequential solder is reflowed under nitrogen, and flux residues are cleaned. The solder volume after reflow will be approximately 50% of the paste volume.
Laser solder ball bumping (SB²)
For rapid prototyping, fine-pitch applica-tions and solder deposition on 3D structures, a novel solder-application technique has been developed and implemented in a production tool. Pre-formed solder balls (spheres), which are available from several suppliers, are singulated and placed on a solderable surface (e. g. Ni/Au bumps). A short laser pulse rapidly melts the solder, leading to an excellent wetting on the substrate. No flux is required since the solder is locally protected by an inert gas (nitrogen). Solder balls can be placed on flat substrates (wafers, single dice, PCBs) as well as on complex 3D structures.
The high-speed machine for solder ball bumping consists of a ball singulation head with z-axis control, the laser for reflow and a precise xy-table for substrate positioning. This machine, which has a speed of 7 balls per second, is applied in industry not only for flip chip applications, but also for a fluxless, low temperature stress solder ball placement in chip size packages (CSP) and for sensor packages.
The main cost advantage of the SB2 compared to stencil printing is the low capital and low set-up cost, since no additional tooling is required. This results in a high flexibility and a fast turnover cycle, because after receipt of wafer, solder bumping can immediately start. Cost calculation show, that solder ball bumping is a competitive method in a production environment, especially if a high flexibility and a fast turnover cycle is required. Due to its high flexibility, the solder ball bumper is also used in our process for repair of defective solder bumps and solder bridges resulting from stencil printing. Compared to copper, nickel has a remarkably lower dissolution rate in molten solder (Ni dissolves by a factor of 30 slower than Cu). Also, the growth rate for the formation of Ni-Sn intermetallics is significantly lower compared to Cu-Sn intermetallics. This shows that Ni has a higher potential for a further reliability improvement – especially for automotive and harsh environment applications than Cu. The use of electroless Ni-bumps in engine control units has been successfully demonstrated.
Multiple reflows using electroless Ni UBM
In a production environment the Ni/solder interface has to withstand several reflows, for example further SMT reflow operations, assembly of BGA, rework. Test dice (2.4mm x 2.4mm) with 64I/Os in area configuration and 300µm pitch (pad size 100µm x 100µm) were used in order to investigate the reliability of soldered FC joints on electroless Ni. By the symmetrical pad design, a simple die-to-die assembly was possible. All dice were plated with 5µm Ni/Au. PbSn61Ag2 solder was applied to some dice by stencil printing. They were placed on the other dice (with Ni/Au only) and reflowed using flux. Each reflow was performed under nitrogen with a peak temperature of 230°C for a period of 40s. The strength of solder joints was tested after 1, 2, 4, 6, 8 and 10 reflows by pulling the dice apart in a tester. For each number of reflows, 4 die-to-die assemblies were tested. The pull forces per FC bump, calculated by dividing the pull force per die by the number of bumps (64 I/O), was always higher than 70g for the 100 x 100µm bumps. Since this test is very sensitive to non-perpendicular pull, the scatter of forces is large. However, the results show that even 10 reflows do not influence significantly the mechanical stability of solder joints on electroless Ni bumps. An additional verification method for flip chips using a torsion tester was applied. The results have revealed better accuracy of the mechanical properties of FC interconnections with our equipment .
Reliability using electroless nickel
A flip-chip assembly using a electroless Ni/Au under bump metallization, and a solder bump applied by stencil printing or SB2 will show comparable basic reliability data as a geometrically equivalent electroplated solder bump. The reliability of FC assemblies is more and more determined by the parameters, yield, quality of the substrate material, design rules of pad opening versus bump size and the properties of the underfill process. A key to the reliability of a flip chip on an organic PCB is the underfill process, the mechanical properties of the underfill material and the flow characteristic, voids, etc. As parameters of the flip-chip assembly process, the fluxes and especially flux residues around the bumps reduce reliability in thermal cycling tests. If the assembly and the underfill process are performed according to the state-of-the-art in industry today, the FC interconnect will withstand 2000 and more thermal cycles. Comparable results are obtained with electroless Ni in combination with isotropic conductive adhesives. These materials are of interest in smart card applications. The mechanical stability of the flip-chip Interconnections during mechanical bowing and torque of the smart-card body is of essential importance.
Using electroless Ni and anisotropic conductive film, the degradation of the contact resistance is due to the properties of the polymeric matrices in the ACF and not determined by the bump material. In these interconnections, thermal cycling turns out to be not as critical as high temperature humidity testing. Thes tests also show that the water absorption of the ACF polymeric matrix determines the reliability. Therefore, from our results it is clear that electroless Ni is a reliable interconnection technique for high-quality flip chip using ACF.
Die Flip-Chip-Technik als Chip-on-Board- oder als Packaging-Technologie findet zunehmend Verbreitung. Wesentlicher Produktionsschritt ist das Aufbringen der Bumps auf den Wafer. Pactech bietet dazu ein Low-cost-Verfahren auf der Basis einer stromlos aufgebrachten Nickel-Gold-Schicht.
La technique des Flip-Chip comme technologie de Chip-on-Board ou de Packaging, est de plus en plus répandue. L’application des bumps sur la tranche de silicium représente une étape majeure de la production. Pactech propose à cet effet un procédé économique basé sur une couche de nickel et d’or appliquée sans courant.
La tecnica Flip-Chip applicata come tecnologia Chip-on-Board o come tecnologia Packaging si trova in una continua fase di diffusione. Il passo di produzione essenziale consiste nell’applicazione dei Bumps sul Wafer. La Pactech a questo proposito offre un procedimento Low-cost sulla base dell’applicazione di uno strato di oro-nichel privo di corrente.