Fab industry is now back in gear again

Happy days are here again – if slightly tinged with a healthy dose of paranoia. Just look at the figures: In 2000, the worldwide markets for fab gear and materials will grow by a whopping 37% – to a total of $35.4bn. To arrive at this official industry consensus forecast, Semi president Stan Myers had to double the projection he wagered earlier this year. And if you want to believe the market researchers at Dataquest, this year’s actual expansion should be more like 69%. Of the market total, according to Semi, assembly and packaging is to grow by 21.5%, to $2.4bn this year. Test gear should be up by 35.5% to $7bn worldwide.

That’s another round of welcome good news after last year’s ramp up of 18.4% – following the 1998 bloodbath of -22% in the wake of the Asianfinancial crisis. It knocked the floor out from under worldwide markets, let prices drop to lowest levels and scrambled all plans for an orderly transition to 300mm wafer processing. And it hastened the pace of consolidation all across the industry.

How long wills the good-luck charm last this time around? Will there be another plus of 23% to live off next year and likewise in 2002, 2003 as Semi projects? Or is, as Wall Street Cassandra Salomon Brothers warns, the semiconductor market so dangerously overheated that it could easily plunge and start the next downturn within the coming six to nine months, ending this year’s euphoria before 2002?

Perhaps the market itself will take care of that: by slowing the torrent of growth to amore sustainable pace through shortages of parts and labor, and by still immature tech-nologies for the build-out of 300mm capacities, and the shrinks to 130nm geometries. „Waferfab capacity will not come on-line as fast as the optimists happen to believe,“ foresees Scott Kulicke from K & S. Developing a new generation of wafer steppers, Kulicke maintains, takes two years at the minimum. All stepper makers, he says, have taken a back seat during the crisis of 1998. That alone should stretch the ongoing boom cycle into the years ahead. Will a more realistic front-end time frame provide relief to the TAP (test, assembly, packaging, the good ol‘ backend) segment, which struggles with its own technology issues and shortcomings? At the moment, packaging drives the semiconductor industry (and is driven itself by the mounting demands of portable consumer communications devices). And it constrains it at the same time: ever smaller package sizes and types (or no packages at all), higher performance functionally and thermally, continuing die shrinks and, going with it, radically higher densities of interconnect.

Semicon West 2000, in its 30th anniversary edition, sporting 1,777 exhibitors (1,174 frontend, 609 backend) and 67,000 attendees, showcased the ongoing „struggle between chips and boards“ deriving from the mismatch between thermal expansion coefficients of silicon die and organic substrates. Adding to that struggle is the growing I/O distribution mismatch between the nanometer geometry of the die and the millimeter realm of the board to get substantial supply power and signal voltages from and to the chip.

Over the next five years, the most challenging issues in assembly and test, as Semi sees them from their worldwide 2400-member perspective, will be: high-density substrates for area-array packaging, the (finally progressing) road barrier of underfill technology, reliability issues of flip chip on organic substrates, and cost-effective cooling mechanisms. In the time frame beyond 2005, it will be the growing distributional gap between die and substrate, an urgently needed integrated approach to chip, system and packaging solutions, the demands of high-frequency processing in telecom gear, and the general manufacturability of larger system-level packages.

In terms of future use of package types, the SOP will clearly dominate the markets by sheer volume, according to IC Insights and the McClean Report. At 40 to 50bn units per year today, SOP usage will reach 69bn units in 2004. Next up in volume will be the PQFP/ PLCC, then at 19.5bn units annually. Fastest growing, albeit from a low starting base, is the BGA from 1.5bn units to more than 9bn in 2004. All others appear stagnating or gradually declining over the next five years. For example, the DIP will come down from more than 10bn packages/year to 6.5bn, but still is a very important technology.

(Werner Schulz)

As test issues grow in importance and test becomes costlier, test technologies and test strategies get closer involved with frontend steps – chip design and wafer processing – as the co-operation agreements between Teradyne and Broadcom, and between Agilent and Qualcomm demonstrate. This applies to integrated manufacturers and chip foundries, says Taylor Driggs of Teradyne, pointing at the 1973JEP platform which is adaptable to various performance parameters. „With the 1973JEP, we are aiming at the subcontracting foundries and at the high-performance microprocessor manufacturers,“ he says. „This involves structured-typed test methods and very high-speed buses to perform the actual testing.“

A highlight of the show: a fully bumped 300mm wafer proudly demoed by Kulicke & Soffa as a result of its flip chip technologies bumping venture with Delphi Delco. The wafer, carrying 600,000 solder bumps to access its 600 devices, is not in production yet but it should be ready, K&S says, when the age of 300mm really begins.

Interesting contrast in approaching test issues in solder-ball X-ray inspection issues: On one side, Nicolet Instruments/GenRad with its low-price range (under $100,00) NXR1500 Plus: Its magnification was improved to 400x to aim it at the newer fine-pitch SMDs, it comes with a sealed or open tube which is fixed. Turning the board accordingly produces the oblique angular inspection views. Feinfocus does it the other way around: its 116.40 system rotates the X-ray tube around the board. „We are first to have this type of imaging in a low price range ($150,000) out in the market,“ says Tony Melton of the US facility. Rotating tube and fixed board leads, of course, to applications with unwieldy, larger boards.

Widely noted for a higher degree of manufacturing flexibility: Esec’s die bonder 2008xP: one platform for different packaging tasks maintained by increased modularity. The gear processes all of today’s popular packaging options (leadframe to BGA) by changing the setup and bonding tools. This reconfigurable setup clearly looks at the Far-East chip-assembly contractors.

Does underfill/adhesive dispensing (precise amount of fluid, capillary effects, timing, temperature, volumetric control) still suffer the image of a pothole, or a barrier, in the road to flip chip and CSP? Not anymore, says Frank Murch of Asymtek, which presented its M2020 dispensing system. „The reality is that materials have improved dramatically in the last two years. Flow-out rates have improved as well, along with new machines. That can speed up production by a factor of 2.“ After the M600, Murch maintains, Asymtek’s M2020 should become the industry benchmark for speed.“The road is open for major advances.“

No higher luminaries than Tom DiStefano and Vern Solberg (of Tessera) chaired a special forum on the viability and performance criteria of the much-anticipated wafer-level packaging as an outgrowth of today’s chip-scale packaging (CSP). No easy answers here, as it turned out. Not even easy answers to what wafer-level packaging (WLP) contains and where the boundaries to chip-scale are. Yet no disagreement among market researchers Jim Walker (Dataquest) and Jan Vardaman (TechSearch International): wafer-level packaging has the potential to do away with „packaging“ as an intermediate production step in IC fabrication.

In the future, as wafer-level packaging develops, so the experts at the forum, packaging will become more of a frontend operation – close to or within the wafer fab. „Wafer-level packaging allows IC components to be shipped directly from the fab fully tested, packaged and ready for mounting by standard surface mount technologies,“ DiStefano foresees. ICs are burned in on the wafer; they are tested only once; power and ground are distributed in the assembled structure, lower I/O counts are possible, and lead inductance is nearly eliminated. In sum: „Wafer-level packaging transforms IC packaging from a labor-intensive process to a batch process much like in a wafer fab.“ This looks like a sea change of semiconductor manufacturing, and it forebodes a definite change in the infrastructure and in the regional make up of the industry, especially as packaging is located in outlying, underdeveloped regions of the world. Coming home to the fab looks like the wave of the future.

One could argue that packaged die is more favorable to high-volume SMT applications. But, as the forum chairs speculated, „some may believe that the ultimate IC package is ’no package‘ – attaching the die directly onto the circuit assembly.“ At this point, of course, all the present reliability issues of underfill come into play and special equipment is needed. Chip-scale, on the other hand, is a proven technology and also viable in space-constrained applications.

But the pace of achieving lighter weight and smaller form factors for consumer goods puts the onus on OEMs to come up with ever more condensed circuit solutions to stay competitive. Compact and mobile electronic appliances such as digital cameras, pagers, palmtops, PADs and phones are clearly the drivers for packaging. With them, the IC evolution ahead is visible: from chip-scale to chip-size, packaged and interconnected through area array directly on the wafer.

(Werner Schulz)

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