Towards wafer-level technology

Christoph Scheiring, Datacon

A lot of innovation is expected from miniaturized applications that are increasingly built in every product of our daily life. These smart devices will probably create high-volume markets. In a downturn, technology development doesn’t stop. Typically, the semiconductor industry tends to increase R&D efforts to develop next generations of semiconductors ready for market introduction in the next upturn. The same is true for the packaging industry. Although the main part of the market is still based on traditional packaging, today more than 800 different packages exist. Area-array methods rapidly gain marketshare as they combine high pin-counts with small footprints. They also allow for custom or semi-custom solutions delivered by assembly subcontractors. As these third-party houses need to offer many different packaging technologies, they increasingly need to rely on assemb-ly equipment suppliers who offer complete solutions with considerable process knowledge.

The trend in semiconductor design drives technology to ever smaller device features, described by Moore’s law, creating ever complex dies with high operating frequencies and pin-counts that exceed 5000 in numbers. (Application-specific flip-chip packages: considerations and options in using FCIP, Paul Mescher et al. Amkor Technology, Pan Pacific Microelectronics Symposium Conference, January 2000.) More functionality can be integrated on a single die, resulting in systems-on-a-chip (SoC). Alternatively, multiple die in combination with passives can be mounted on a common substrate and assembled together in a single package (system-in-a-package, SiP). New interconnect technologies are required to interconnect the die with the package. Flip-chip is the technology of choice in many cases as it provides a short interconnect distance and allows for redistribution of bonding paths over the package surface.

With increasing chip and package complexity, the interface between both is starting to blur. Recent developments are directed towards a higher degree of integration between die and package, or package and board. Wafer-level packaging (WLP) applies front-end processing techniques to the backend (assembly) part. WLP involves packaging steps of the individual die while they are still on the wafer. It’s a fast accelerating trend and will have a large impact on the manufacturing process.

Performance and form factor continue to drive these trends. Although multi-chip modules or other forms of SiP provide an answer to more systems integration, in many cases they do not allow for very small footprints in a number of applications. One example is the stacked-die technology. This package is in large part driven by the miniaturization demand where the device size plays an important role. Stacking multiple die on top of each other allows for considerable smaller footprints as compared to already compact multi-chip modules. On the other hand, the height (Z-dimension) of the package comes into play here. In many applications, the height of a package needs to be as thin as possible. Other challenges in stacking die include the bonding of the different die on top of each other, and the technology for connecting all bond paths to the package substrate. Still, the system-in-a-package approach might be the only way from manufacturing viewpoint, e.g. when combining chips that have different manufacturing requirements. An example is the combination of power ICs, which need few masks but take up considerable space, with logic, which typically requires many masking steps but usually have a small footprint. The only way there is to separate the production of these building blocks completely, and assemble them into multi-chip packages.

One of the critical aspects of ultra-thin packages is die thickness, because wa-fers have to be thinned before they canbe assembled down to 120µm or 100µm using back grinding. These ultra-thin so-lutions require an optimized process to provide a rest thickness below 50µm. Processing and handling these thinned wa-fers can be really tricky and requires special expertise.

The advantages of thin wafers are multiple: space saving, better heat dissipation and full exploitation of the flexibility of the silicon. Wafer thicknesses as low as 40µm have already been tested in applications. Even 10µm can be achieved in lab environment. The crucial point is that the thinning process must be inexpensive enough to allow cost-efficient volume production of applications like the „intelligent“ label so that they will partly replace barcodes on paper. Structured, fragile silicon wafers can be made so thin that they can be rolled without suffering damage.

Ultra-thin packaging combined with flexible assemblies will not only improve existing products, but will also enable up to now unseen solutions with hidden electronics. They can be mounted into mobile gear to increase system integration. Or they can be applied in devices that mo-nitor health or improve daily life where size really matters, such as hearing aids. Another application area is flexible devices. Using ultra-thin silicon, flexibleassemblies can be developed, e.g. forchip-on-flex, chip-in-paper or chip-in-board for identification systems. In order to provide such a technology aimed at low-cost manufacture, the process mustbe optimized and equipment need to be adapted.

Volume production of ultra-thin packages poses strong requirements on reliability and yield, and compels in-depth knowledge of the material properties of ultra-thin silicon. That’s why much effort in the development of a reliable thinning process must be directed towards detailed investigation of the performance of the ultra-thin wafer under bending stress and analysis of long-term behavior and reliability. As wafers are further thinned down, they become more fragile for subsequent treatments such as transfer and mounting. Industrial techniques need to be developed for these wafers. Thinning, handling and shipping techniques are only the first steps. To fully exploit the advantages of thin and flexible chips, innovative high-density packaging concepts leading to paper-thin assemblies need to be designed.

Datacon decided years ago to start strategic research towards novel ultra-thin packaging solutions and their adaptation by manufacturing equipment. Three technologies were targeted: multi-chip-module with active component integration into flexible substrates (MCM-L), chip-on-chip and chip-in-paper. The MCM-L technology can optimize telecommunication gear towards portability and performance. Chip-on-chip will enable improved medical applications such as hearing aids, and hidden identification systems will become reality by using chip-in-paper or chip-in-foil methods.

To develop these innovative solutions, the company focuses on pick&place of ultra thin dies both for die attach and flip-chip assembly. In addition, thin-wafer han-dling techniques were considered. Ultra-thin packages were devel-oped, and small-gap, flip-chip technologies are realized to perform interconnections. And last but not least, test methods are improved.

Wafers can be thinned to 50µm or below through grinding, plasma or wet etching. An important aspect of the thinning operation is that the wafers remain strong enough, so that fewer wafers and dies are lost due to breakage. This increases fab yield and productivity. During and after the thinning processes, the wafers are fragile and susceptible to handling damage. Datacon targets the realization of specific handling and mounting techniques based on existing standard equipment. Providing a classical wafer mounter for some years and currently investigating to adapt this, so that is more tailored to the thin-wafer die-bond process. To cope with the fragility of wafers and dies, for the transport ways of sticking the wafer onto some kind of foil or material are investigated. Ejection of the die with the traditional needle ejector is now subject to limitation because the chip can be easily damaged. Besides that, we are considering a method that works with reusable backing materials.

EPP 189

Viel verspricht man sich von künftigen papierdünnen und flexiblen Chips in hochvolumigen Applikationen. Solche Consumer-Produkte wie ID- oder Waren-Label aller Art müssen natürlich äußerst kostengünstig hergestellt werden. Andererseits sind solche bis unter 50 µm Dicke herabgedünnten Wafer und Dies sehr empfindlich während der Bearbeitung. Die Frage ist: welche Entwicklungen werden Mainstream?

On attend beaucoup des puces fines comme du papier et souples dans les applications à grand volume. Les produits de consommation comme les étiquettes d’identification ou de prix doivent bien sûr être produits de manière extrêmement peu coûteuse. Par ailleurs, les wafers et les dies réduits à des épaisseurs inférieures à 50 µm sont particulièrement fragiles durant la fabrication. La question est donc de savoir quels développements prendront le dessus.

Dai futuri e sottilissimi chips per applicazioni di massa ci si aspetta molto. Simili prodotti di consumo quali etichette di qualsiasi tipo per ID o per prodotti devono essere naturalmente prodotte in maniera più economica possibile. D’altra parte, i Wafer e i Dies assottigliati sino ad uno spessore di meno di 50 µm sono molto sensibili agli interventi di lavorazione. La domanda é: quali sviluppi diventeranno Mainstream?